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PLL702-06
Clock Generator for Printer Applications
FEATURES
* * * * * * *
*
PIN CONFIGURATION
XIN XOUT VDDA VDDD GNDUSB VDDUSB USB/USB_SEL * VDDCPU
T
1 CPU Clock output with selectable frequencies (50, 66.67, 75, 80, 83.3, 90, 100,125 or 133 MHz). 1 Selectable 48, 30 or 12MHz USB Clock output. Selectable Spread Spectrum (SST) for EMI reduction on CPU clock. PowerPC compatible CPU Clock. Advanced, low power, sub-micron CMOS processes. 14.31818MHz fundamental crystal input. 3.3V and/or 2.5V operation. Available in 16-Pin 150mil SOP.
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
FS0T FS1T SS0^ SS1^ GNDA GNDD GNDCPU CPU
Note : ^: Internal pull-up resistor T: Tri-level Input
*: Bi-directional pin
DESCRIPTION
The PLL702-06 is a low cost, low jitter, and high performance clock synthesizer for generic Printer applications. It provides one CPU clock and a selectable 48, 30 or 12MHz (USB) output. The user can choose among 9 different clock frequencies and 3-selectable downspread Spread Spectrum modulation to reduce EMI on CPU clock. All frequencies are generated from a single low cost 14.31818MHz crystal. CPU clock can be driven from an independent 2.5V or 3.3V power supply.
CPU CLOCK FREQUENCY TABLE
FS1
0 0 0 M M M 1 1 1
PLL702-06
FS0
0 M 1 0 M 1 0 M 1
CPU (MHz)
50 66.67 75 80 83.33 90* 100 125 133*
*Notes: Actual CPU frequency for 90Mhz is 88.88Mhz, 133Mhz is 130.9Mhz
BLOCK DIAGRAM
USB_SEL XIN XOUT
Control Logic XTAL OSC VDDUSB USB
PLL
SS(0:1) FS(0:1)
Control Logic
PLL SST
VDDCPU CPU
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/26/05 Page 1
PLL702-06
Clock Generator for Printer Applications
PIN DESCRIPTIONS
Name
XIN XOUT VDDA VDDD GNDA GNDD VDDUSB VDDCPU GNDUSB GNDCPU USB / USB_SEL CPU SS(0:1) FS(0:1)
Number
1 2 3,4,11,12
Type
I O P
Description
Crystal input to be connected to a 14.31818MHz fundamental crystal (CL = 20pF, parallel resonant mode). Load capacitors have been integrated on the chip. No external Load capacitor is required. Crystal Output 3.3V power supply and GND.
5,6,8,10
P
CPU and USB outputs have separate power supply pins (VDD and GND). VDDCPU can accept 3.3V and/or 2.5V power supply. Bi-directional pin. Upon power-on, the value of USB_SEL is latched in and used to select the USB output (see USB selection table below). After the input has been latched-in, the pin serves as USB (48, 30 or 12 MHz) output. 0=15k to GND, M=leave open, 1=15k to VDD_USB CPU clock signal output pin. The CPU clock frequency is selected as per the frequency table on page 1, depending on the value of FS(0:1). Bi-level input with internal Pull-up resistor for SST control (see Spread Spectrum selection table on p.2). 0=connect to GND, 1=leave open (or to VDD). Tri-level inputs for CPU clock frequency selection (see table on p.1). 0=connect to GND, M=not connected, 1=connect to VDDA.
7
B
9 13,14 15,16
O I I
USB FREQUENCY TABLE
USB_SEL
0 M 1
USB
48 MHz 30 MHz 12 MHz
SPREAD SPECTRUM SELECTION TABLE
SS1
0 0 1 1
SS0
0 1 0 1
Spread Spectrum Modulation
OFF - 0.50% - Down Spread - 1.00% - Down Spread - 1.25% - Down Spread
www.phaselink.com
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
Rev 10/26/05 Page 2
PLL702-06
Clock Generator for Printer Applications
FUNCTIONAL DESCRIPTION Tri-level and two-level inputs
In order to reduce pin usage, the PLL702-06 uses tri-level input pins. These pins allow 3 levels for input selection: namely, 0 = Connect to GND, 1 = Connect to VDD, M = Do not connect. Thus, unlike the two-level selection pins, the tri-level input pins are in the "M" (mid) state when not connected. In order to connect a tri-level pin to a logical "zero", the pin must be connected to GND. Likewise, in order to connect to a logical "one", the pin must be connected to VDD.
Internal to chip VDD
External Circuitry
Rup Power Up Reset
R RB
Output
EN
Bi-directional pin
Clock Load
Latched Input
Latch
RUP/4
Jumper options
NOTE: Rup=Internal pull-up resistor (see pin description). Power-up Reset : R starts from 1 to 0 while RB starts from 0 to 1.
BI-DIRECTIONAL PINS WITH INTERNAL PULL-UP
Connecting a bi-directional pin
The PLL702-06 also uses bi-directional pins. The same pin serves as input upon power-up, and as output as soon as the inputs have been latched. The value of the input is latched-in upon power-up. Depending on the pin (see pin description), the input can be tri-level or a standard two-level. Unlike unidirectional pins, bi-directional pins cannot be connected directly to GND or VDD in order to set the input to "0" or "1", since the pin also needs to serve as output. In the case of two level input pins, an internal pullup resistor is present. This allows a default value to be set when no external pull down resistor is connected between the pin and GND (by definition, a tri-level input has a default value of "M" (mid) if it is not connected). In order to connect a bi-directional pin to a non-default value, the input must be connected to GND or VDD through an external pull-down/pull-up resistor.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/26/05 Page 3
PLL702-06
Clock Generator for Printer Applications
Note: when the output load presents a low impedance in comparison to the internal pull-up resistor, the internal pull-up resistor may not be sufficient to pull the input up to a logical "one", and an external pull-up resistor may be required. For bi-directional inputs, the external loading resistor between the pin and GND has to be sufficiently small (compared to the internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical "zero"). In order to avoid loading effects when the pin serves as output, the value of the external pull-down resistor should however be kept as large as possible. In general, it is recommended to use an external resistor of around one sixth to one quarter of the internal pull-up resistor (see Application Diagram).
VDD Power Up Ramp Requirements:
At startup, the chip reads a lot of settings for operation according to the application's requirements. Since reading the settings is done only at startup and then frozen for the time of operation, it is important that the power-up environment is somewhat controlled to facilitate proper reading of the settings. The important VDD pins are VDDA (Pin3) and VDDD (Pin4) and they should apply to the following two-startup requirements: * * * VDDD should be equally fast or slower than VDDA. VDDD performs a chip reset when VDD has reached a certain level and VDDA should have reached at least up to the same level as well to properly process the reset. The VDD Power Up Ramp of VDDD and VDDA should pass through the section 1.8V to 2.5V no faster than 100s and with a continuously increasing slope. In this section the tri-level select inputs are read. After VDD Power off, VDD should be allowed to go to 0V and stay there for at least 1ms before a new VDD Power on. It is important that proper preconditions exist at every startup. Remaining charges in the chip or in circuit filter capacitors may interfere with the preconditions so it is important that VDD has been at 0V for some time before each startup.
VDD off
3.3V
2.97V 2.5V 2.2V
1.8 V
VDD on
GND (0V)
No limit
Reset enable
Min 1ms
>100us
Reset disable
Min 1s
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/26/05 Page 4
PLL702-06
Clock Generator for Printer Applications
Electrical Specifications
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model
SYMBOL
V DD VI VO TS TA TJ
MIN.
-0.5 -0.5 -65 0
MAX.
4.6 V DD +0.5 V DD +0.5 150 70 125 260 2
UNITS
V V V C C C C kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied.
2. AC Specifications PARAMETERS
Crystal Input Frequency SST modulation sweep rate Output Rise Time Output Fall Time Duty Cycle Max. Absolute Period Jitter Max. Jitter, cycle to cycle 0.8V to 2.0V with no load 2.0V to 0.8V with no load At VDD/2 Long term, No SST Long term + Short term 45 50
CONDITIONS
MIN.
TYP.
14.31818 28
MAX.
UNITS
MHz kHz
1.5 1.5 55 180 150
ns ns % ps ps
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/26/05 Page 5
PLL702-06
Clock Generator for Printer Applications
3. DC Specifications PARAMETERS SYMBOL
VDDA VDDD Operating Voltage VDDUSB VDDCPU V IH V IL V IH V IL V IH V IL V OH V OL V OH I out I DD IS No Load For all Tri-level input For all Tri-level input For all normal input For all normal input I OH = -25mA VDD = 3.3V I OL = 25mA I OH = -8mA VDD-0.4 25 30 100 2.4 0.4 2 0.8 VDD-0.5 0.5
CONDITIONS
Nominal voltage is 3.3V Nominal voltage is 2.5V Nominal voltage is 3.3V
MIN.
2.97 2.25 2.97
TYP.
MAX.
3.63 2.75 3.63
UNITS
V V V V
Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output High Voltage At CMOS Level Nominal Output Current Operating Supply Current Short-circuit Current
VDD/2 VDD/2 VDD/2 - 1
V V V V V V V V mA mA mA
4. Crystal Specifications PARAMETERS
Crystal Resonator Frequency Crystal Loading Rating Recommended ESR
SYMBOL
F XIN C L (xtal) RE
CONDITIONS
Parallel Fundamental Mode
MIN.
TYP.
14.31818 21
MAX.
UNITS
MHz pF
AT cut
30
Note: A detailed crystal specification document is also available for this part.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 10/26/05 Page 6
PLL702-06
Clock Generator for Printer Applications
LAYOUT RECOMMENDATION
The following is the recommended layout for PhaseLink's PLL702-06 in 16-pin SOIC package.
PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION The following guidelines are to assist you with a performance optimized PCB design:
- Keep all the PCB traces to PL702-06 as short as possible, as well as keeping all other traces as far away from it as possible. - Place the crystal as close as possible to both crystal pins of the device. This will reduce the cross-talk between the crystal and the other signals. - Separate crystal pin traces from the other signals on the PCB, but allow ample distance between the two crystal pin traces. - Place 0.01F~0.1F decoupling capacitors between VDDs and GNDs (see above diagram), on the component side of the PCB, close to the VDD pins. It is not recommended to place these components on the backside of the PCB. Going through vias will reduce the signal integrity, causing additional jitter and phase noise.
- It is highly recommended to keep the VDD and GND traces as short as possible. - When connecting long traces (> 1 inch) to a CMOS output, it is important to design the traces as a transmission line or `stripline', to avoid reflections or ringing. In this case, the CMOS output needs to be matched to the trace impedance. Usually `striplines' are designed for 50 impedance and CMOS outputs usually have lower than 50 impedance so matching can be achieved by adding a resistor in series with the CMOS output pin to the `stripline' trace. - Please contact PhaseLink for the application note on how to design outputs driving long traces or the Gerber files for the PL702-06 layout. - Please contact PhaseLink for a detailed crystal spec.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 10/26/05
www.phaselin.com
Rev.
PLL702-06
Clock Generator for Printer Applications
PACKAGE INFORMATION
16 PIN Narrow SOIC ( mm )
SOIC Symbol A A1 B C D E H L e Min. Max. 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 10.00 9.80 3.80 4.00 5.80 6.20 0.40 1.27 1.27 BSC
E H
D
A1 B
A C L e
ORDERING INFORMATION
For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following: Device number, Package type and Operating temperature range
PLL702-06 X X X X
PART NUMBER NONE= TUBE R= TAPE AND REEL
NONE= NORMAL PACKAGE L= GREEN PACKAGE
PACKAGE TYPE S=SOP Part / Order Number PLL702-06SC-R PLL702-06SC PLL702-06SCL-R PLL702-06SCL Marking P702-06SC P702-06SC P702-06SCL P702-06SCL SOP SOP SOP SOP
TEMPERATURE C=COMMERCIAL Package Option -Tape and Reel -Tubes -Tape and Reel Green -Tubes Green Temperature 0 to +70C 0 to +70C 0 to +70C 0 to +70C
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 10/26/05 Page 8

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